Due to the ever-growing requirements in high performance data computation, multiprocessor systems have been proposed\r\nto solve the bottlenecks in uniprocessor systems. Developing efficient multiprocessor systems requires effective exploration of\r\ndesign choices like application scheduling, mapping, and architecture design. Also, fault tolerance in multiprocessors needs to\r\nbe addressed. With the advent of nanometer-process technology for chip manufacturing, realization of multiprocessors on SoC\r\n(MpSoC) is an active field of research. Developing efficient low power, fault-tolerant task scheduling, and mapping techniques\r\nforMpSoCs require optimized algorithms that consider the various scenarios inherent in multiprocessor environments. Therefore\r\nthere exists a need to develop a simulation framework to explore and evaluate new algorithms on multiprocessor systems. This\r\nwork proposes amodular framework for the exploration and evaluation of various design algorithms forMpSoC system.This work\r\nalso proposes new multiprocessor task scheduling and mapping algorithms for MpSoCs. These algorithms are evaluated using\r\nthe developed simulation framework. The paper also proposes a dynamic fault-tolerant (FT) scheduling and mapping algorithm\r\nfor robust application processing. The proposed algorithms consider optimizing the power as one of the design constraints. The\r\nframework for a heterogeneous multiprocessor simulation was developed using SystemC/C++ language. Various design variations\r\nwere implemented and evaluated using standard task graphs. Performance evaluation metrics are evaluated and discussed for\r\nvarious design scenarios.
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